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Reversible Full Adder/Subtractor

Abstract:

This paper proposes two novel designs of Adder/Subtractor using reversible logic gates. The first design is an implementation of two's complement Adder/Subtractor suitable for signed/unsigned numbers. The other design proposes a novel reversible gate that can work singly as a reversible Full Adder/Subtractor unit. The proposed Full Adder/Subtractor is then applied to design a reversible 4-bit ripple Adder/Subtractor.

Published in: 2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)

Date of Conference: 04-06 October 2010

Date Added to IEEE Xplore: 17 December 2010

ISBN Information:

DOI: 10.1109/SM2ACD.2010.5672298

Conference Location: Gammarth, Tunisia

I. Introduction

Reversible computing is a promising area of a study. According to Landauer's research, the amount of energy dissipated per irreversible bit operation in thermodynamic entropy is at least kT ln2 joules, where k is Boltzmann's constant, and T is the temperature of the environment[1] [4]. Bennet [8] argued that energy dissipation would be zero only if the network consists of reversible gates, so reversible computing will become very important on the future days in circuit design.

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