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FPGA-Supported HDL Approach to Implement Reversible Logic Gate-Based ALU

Abstract:

This manuscript banks on the design of reversible gates and implementation of an Arithmetic Logic Unit – 16 bit (ALU) utilizing Verilog with Xilinx ISE 14.7, Spartan 6FPGA kit. The same functionality is compared with a basic logic gate- based ALU. Reversible gates can produce a distinct output vector from each input vector, and the opposite is also possible. Circuits with irreversible gates suffer from data erosion. Power loss results from a circuit’ s loss of data. In conclusion, gates with reversible logic are preferable over irreversible counterparts. A library of reversible gates, comprising of AND, OR, NAND, NOR, and XOR, using Verification Logic Hardware Description Language (HDL) is developed, which in turn contributes to the designing of arithmetic and combinational logic like full adder, decoder (2: 4), decoder (3: S), multiplier, full subtractor, and comparator.

Published in: 2023 11th International Conference on Internet of Everything, Microwave Engineering, Communication and Networks (IEMECON)

Date of Conference: 10-11 February 2023

Date Added to IEEE Xplore: 11 April 2023

ISBN Information:

DOI: 10.1109/IEMECON56962.2023.10092307

Conference Location: Jaipur, India

I. Introduction

Modern computers squander a lot of power and storage space. Every instant, they discard millions of bits. These are built on irreversible logic units, which have been Acknowledged for a significant period to be essentially wasteful energy-wise. The optimum solutions are hence reversible gates. Losses are kept to a minimum in circuits with reversible gates. The number of inputs and outputs in these circuits will be identical, and the vectors of inputs and outputs will be mapped one to one [1]. Examples of such gates are Fredkin, Toffoli, Interaction, and Switch.

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